𒀹insignificant thoughts𒀺 on Nostr: LisPi I am not sure how it actually works, so I am wildly speculating here. I was ...
LisPi (nprofile…2mzm) I am not sure how it actually works, so I am wildly speculating here. I was under the assumption that the error correction bits are accessed at the same time as the data bits through a wider bus, so if the memory doesn't have those bits I would assume it would need to do another memory access to read/store the correction bits, thus I think that doing it without memory support would be slowing down memory access dramatically.
Though on second thought I think that if the CPU was designed from to accept a narrower memory bus then it might be able to dedicate some of it to ECC, only losing a small amount of throughput, but I don't know enough about micro architecture design to conclude if that would be a small change to the memory controller or require a redesign of large parts of the cpu. I think DDR5 has a 64 bit memory bus, so if that gets reduced to 56bits with 8 bits for ECC then that would also mean that reading a 64bit integer would require two memory reads.
Though on second thought I think that if the CPU was designed from to accept a narrower memory bus then it might be able to dedicate some of it to ECC, only losing a small amount of throughput, but I don't know enough about micro architecture design to conclude if that would be a small change to the memory controller or require a redesign of large parts of the cpu. I think DDR5 has a 64 bit memory bus, so if that gets reduced to 56bits with 8 bits for ECC then that would also mean that reading a 64bit integer would require two memory reads.