Andrew Zonenberg on Nostr: Anyone ( nprofile1q…ydpy5 or nprofile1q…a25rk maybe?) have recommendations for ...
Anyone ( nprofile1qy2hwumn8ghj7un9d3shjtnddaehgu3wwp6kyqpq7wkkj73azdfr23hmgd07fn0h39xvy0w72garahk5p8hg8jv8dx5snydpy5 (nprofile…dpy5) or nprofile1qy2hwumn8ghj7un9d3shjtnddaehgu3wwp6kyqpqccvvkmx4xqyaqdzpd90ycuavhctfrq23qpaftqlrr0vvh6u2rpksea25rk (nprofile…25rk) maybe?) have recommendations for power decoupling a 32-bit LPDDR4? Not seeing any good vendor guidance from ST or Kingston (my SoC and memory vendor respectively), or maybe I'm just reading the wrong docs.
My general go-to for a chip this big and fast would be at least two 4.7 uF 0603 per rail plus one 0.47 uF 0402 per VDDQ/VDD1/VDD2 ball. I may find myself shrinking some of the small caps to 0201 due to the BGA pitch (0.65 x 0.8 mm) but the ballout does look pretty decoupling-friendly so that's in my favor.
My general go-to for a chip this big and fast would be at least two 4.7 uF 0603 per rail plus one 0.47 uF 0402 per VDDQ/VDD1/VDD2 ball. I may find myself shrinking some of the small caps to 0201 due to the BGA pitch (0.65 x 0.8 mm) but the ballout does look pretty decoupling-friendly so that's in my favor.