Amini Allight on Nostr: I'm curious: does anyone know what this synthesizes to, if it's synthesizable at all ...
I'm curious: does anyone know what this synthesizes to, if it's synthesizable at all
Verilator simulates it setting the "out" register 1 clock earlier than non-blocking assignment, but when I run it through Vivado it seems to synthesize it with two registers like non-blocking
#verilog #fpga #hardware
Published at
2024-09-02 19:42:20Event JSON
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