Andrew Zonenberg on Nostr: Is anybody interested in collaborating on an informal spec + reference implementation ...
Is anybody interested in collaborating on an informal spec + reference implementation for tunneling AMBA over a single high speed serial link?
Think AMBA CHI C2C or PCIe stripped down to its bare essentials.
Basic concepts I have in mind:
* No link training or negotiation. Both sides must agree on data rate out of band or hard-code
* No plug-and-play enumeration, device descriptors, hotswap support, etc. Intended for hard wired applications between multiple FPGAs (or potentially FPGA-ASIC in the future)
* Capable of being used with FPGA LVDS GPIOs or gigabit transceivers depending on data rate
* Point to point topology only at the physical/link layer. Multiple links can be instantiated to build star/tree structures as needed.
* 8B/10B line code
* Transports raw AMBA requests/responses. Initial implementation will be APB only, but intent is to support encapsulation of AHB/AXI-stream/AXI in the future
Think AMBA CHI C2C or PCIe stripped down to its bare essentials.
Basic concepts I have in mind:
* No link training or negotiation. Both sides must agree on data rate out of band or hard-code
* No plug-and-play enumeration, device descriptors, hotswap support, etc. Intended for hard wired applications between multiple FPGAs (or potentially FPGA-ASIC in the future)
* Capable of being used with FPGA LVDS GPIOs or gigabit transceivers depending on data rate
* Point to point topology only at the physical/link layer. Multiple links can be instantiated to build star/tree structures as needed.
* 8B/10B line code
* Transports raw AMBA requests/responses. Initial implementation will be APB only, but intent is to support encapsulation of AHB/AXI-stream/AXI in the future