shac ron ₪‎ on Nostr: How do you fix #RISCV to have good performance? Let's see how the people at ...

How do you fix #RISCV to have good performance? Let's see how the people at #Tenstorrent do it:

rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_zifencei_zihintntl_zihintpause_zimop_za64rs_zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b

Easy, just keep adding instructions until you have a good ISA.

Some of these are:
zba - Address calculation extension.
zbb - Basic bit manipulation extension.
zicond - Integer conditional operations extension.
zbs - Single-bit operation extension.
zvbb - Vector basic bit-manipulation extension.
zicbom - Cache-block management extension.
zicbop - Cache-block prefetch extension.
zicboz - Cache-block zero extension.
zcb - Simple compressed instruction extension.
ziccif - Main memory supports instruction fetch with atomicity requirement.
ziccamoa - Main memory supports all atomics in A
zicclsm - Main memory supports misaligned loads/stores.
ziccrse - Main memory supports forward progress on LR/SC sequences.
zicsr - Control and status register access extension.
zifencei - Instruction-fetch fence extension.
zihintntl - Non-temporal locality hints extension.
zihintpause - Pause hint extension.
zawrs - Wait-on-reservation-set extension.