48kRAM but with parity on Nostr: Ah! Totally different context, indeed. Here I agree with Stefany Allaire's approach ...
Ah! Totally different context, indeed. Here I agree with Stefany Allaire's approach on her designs where the chip is designed and documented as though it were an ASIC but gets implemented on the FPGA. It doesn't receive upgrades like the firmware does. And it's functionality is well defined. I have ZERO issues with that for a "modern retro" system.
Published at
2024-05-01 20:55:09Event JSON
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