Event JSON
{
"id": "784a3b76df9861a0fe4b3e1b4c8f178c89118dc51b7b81b31280f1e553905ce4",
"pubkey": "e4769a394a68e04a6550cd793ea2f27628a4af204b3e2504ad8e09ecab8ba584",
"created_at": 1690794827,
"kind": 1,
"tags": [
[
"p",
"9b1e0c6d0dbb1f3de564baab967fbd107b7fdd372f05518fcc76f9f829c42849",
"wss://relay.mostr.pub"
],
[
"p",
"79c4b3e2b1e7d8d74fa652cdc1dee37f9cd08fefdc13a79f8d1146c0b69fd1fb",
"wss://relay.mostr.pub"
],
[
"p",
"c5cf39149caebda4cdd61771c51f6ba91ef5645919004e5c4998a4ea69f00512",
"wss://relay.mostr.pub"
],
[
"p",
"588da04a36777f3e73257ee2e3f8624cbb4520ea6bcde9951ad106dd0941bbe4",
"wss://relay.mostr.pub"
],
[
"e",
"37e4c0072b836555f15ab33e7e2689a050216a49f9efd8a26b5650bb540fa6ab",
"wss://relay.mostr.pub",
"reply"
],
[
"mostr",
"https://pleroma.nobodyhasthe.biz/objects/9e345be1-d6db-4ba0-a8ae-571535f0df97"
]
],
"content": "nostr:npub1nv0qcmgdhv0nmetyh24evlaazpahlhfh9uz4rr7vwmuls2wy9pys7hskkw nostr:npub108zt8c43ulvdwnax2txurhhr07wdprl0msf608udz9rvpd5l68ascvdkr5 nostr:npub1ch8nj9yu4676fnwkzacu28mt4y002ezeryqyuhzfnzjw560sq5fqaysw60 the ECC in ddr5 is basically signal correction, it's not the same ECC as you would have in ECC DDR RAM. Generally (I haven't done enough reading into DDR5), there's a whole chip that does nothing but keep parity information.\n\nIf DDR5 RAM chips are failing, they fail like you're used to.",
"sig": "3f9c42778a207b171379bdbafa76233341a251a0b04150f1ecce4487a31eaa412aa79b244a76811bd81c585825d419727b92e362a53b8023789447d8a80b2397"
}
