Semisol 👨💻 on Nostr: Verilog is like C but VHDL is some abomination that is like C++ and Java You should ...
Verilog is like C but VHDL is some abomination that is like C++ and Java
You should absolutely use FuseSoC. It makes it *very* easy to interface with whatever tools of your choice + package management of sorts.
Currently developing for an iCE40 UP5K with Verilog, so Yosys for synthesis and nextpnr/icestorm for the FPGA bitstream generation.
iCE40 UltraPlus is nice as they are pretty cheap, they have 1024Kbit in 4 large RAM blocks, and a RE’d open source toolchain that works great.
If you insist on using VHDL there is this: https://github.com/ghdl/ghdl-yosys-plugin
You should absolutely use FuseSoC. It makes it *very* easy to interface with whatever tools of your choice + package management of sorts.
Currently developing for an iCE40 UP5K with Verilog, so Yosys for synthesis and nextpnr/icestorm for the FPGA bitstream generation.
iCE40 UltraPlus is nice as they are pretty cheap, they have 1024Kbit in 4 large RAM blocks, and a RE’d open source toolchain that works great.
If you insist on using VHDL there is this: https://github.com/ghdl/ghdl-yosys-plugin